1. Field of the Invention
The invention relates generally to semiconductor fin structures. More particularly, the invention relates to semiconductor fin structures with enhanced performance.
2. Description of the Related Art
Semiconductor circuits typically include both active semiconductor devices, such as but not limited to transistors and diodes, as well as passive devices, such as but not limited to resistors and capacitors. As semiconductor technology has advanced over several decades, both the active semiconductor devices and the passive devices have conventionally been scaled to increasingly smaller dimensions to reduce costs.
In an effort to provide for continued scaling of semiconductor structures to continuously smaller dimensions while maintaining or enhancing semiconductor device performance, the design and fabrication of semiconductor fin devices and semiconductor fin structures has recently evolved within the semiconductor fabrication art. Semiconductor fin devices and semiconductor fin structures, and in particular finFET devices and finFET structures, typically comprise vertical semiconductor channel structures that are fabricated using a semiconductor fin (i.e., including a vertical semiconductor surface rather than a planar semiconductor surface relative to a plane of a semiconductor substrate) as a channel region for the semiconductor fin devices and the semiconductor fin structures. Within the context of a finFET structure, a gate dielectric is located upon at least one vertical surface of the semiconductor fin. An inverted U shaped gate electrode is then located over the gate dielectric and the semiconductor fin. Since the sidewall surfaces, and sometimes also the top surface, of the semiconductor fin primarily comprise a channel region of the finFET structure, a finFET structure may in general may be scaled with increased channel dimensions in a vertical direction, to provide a constant or enhanced channel area of the finFET structure while decreasing an aerial surface area requirement of the finFET structure. finFET structures certainly provide advantages within semiconductor device fabrication and semiconductor structure fabrication since finFET structures allow for constant or increased channel region areas within finFET structures while using decreased semiconductor substrate areas when fabricating the finFET structures.
Various finFET structures having desirable properties, and methods for fabricating those finFET structures, are known in the semiconductor fabrication art.
For example, Fried et al., in U.S. Pat. No. 6,664,582, teaches a finFET structure integrated with a fin-capacitor structure to provide a semiconductor fin memory structure. By integrating the finFET structure with the fin-capacitor structure, the semiconductor fin memory structure may be fabricated with improved semiconductor fin memory structure density without overly increasing fabrication cost and complexity of the semiconductor fin memory structure.
In addition, Joshi et al., in U.S. Pub. No. 2005/0017377 and U.S. Pat. No. 6,921,982, teaches a semiconductor fin structure, such as a finFET structure, that includes a semiconductor fin that includes a semiconductor channel comprising a semiconductor channel core layer having a semiconductor channel envelope layer laminated thereto that has a different lattice structure than the semiconductor channel core layer. The different lattice structures for the semiconductor channel core layer and the semiconductor channel envelope layer provide a lattice mismatch therebetween that in turn introduces a strain into the semiconductor channel within the semiconductor fin structure.
Further, Zhu et al., in U.S. Pub. No. 2005/0239242, teaches a semiconductor fin structure, such as a finFET structure, that includes a plurality of stacked semiconductor fins. The plurality of stacked semiconductor fins within the semiconductor fin structure allows for improved circuit density while accommodating mobility differences within n-finFET and p-finFET devices that may be fabricated using the plurality of stacked semiconductor fins within the context of a single semiconductor substrate.
Still further, Fischer et al., in U.S. Pub. No. 2006/0022248, teaches a semiconductor fin structure, such as a finFET structure, having a gate that controls only a central region of a semiconductor fin within the semiconductor fin structure. Such gate control over only a limited portion of the semiconductor fin minimizes undesirable leakage paths within a semiconductor fin device that comprises the semiconductor fin structure.
Finally, Manger in U.S. Pat. No. 7,074,660, teaches a finFET structure, and a method for fabricating the finFET structure, that allows for an enhanced aerial density of a plurality of finFET devices within the finFET structure. The foregoing enhanced aerial density of the finFET devices within the finFET structure is provided by using a non-photolithographic method for fabricating a plurality of contacts within the plurality of finFET devices.
Semiconductor fin devices and structures, such as in particular finFET devices and structures, are certain to become increasingly prominent as semiconductor technology advances. Thus, desirable are semiconductor fin devices and structures having enhanced performance and enhanced functionality, and methods for fabrication thereof.